Semiconductor memory devices for storing data can typically be categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, however nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Thus, nonvolatile memory devices are widely used in applications where the possibility of power supply interruption is present.
Conventional nonvolatile memory devices include a type of electrically erasable programmable read only memory (EEPROM) device typically referred to as a flash EEPROM device. Flash EEPROM devices typically include a semiconductor substrate of first conductivity type (e.g., P-type), spaced source and drain regions of second conductivity type (e.g., N-type) in the substrate, a channel region at a face of the substrate, between the spaced source and drain regions, a floating gate for storing charge carriers when the device is programmed and a control gate which overlies the floating gate, opposite the channel region. Operation of a flash EEPROM device is typically divided into three modes including programming, erasing and reading.
A flash EEPROM device is typically programmed by biasing the drain region to a first positive bias, relative to the source region, and biasing the control gate to a second positive bias which is greater than the first positive bias. In the absence of any stored charge on the floating gate, these biases cause the formation of an inversion-layer channel of electrons at the face of the substrate, between the source and drain regions. As will be understood by those skilled in the art, the drain-to-source voltage establishes a lateral electric field in the substrate and accelerates the electrons across the channel to the drain region where they acquire sufficiently large kinetic energy and are typically referred to as "hot" electrons. The larger positive bias on the control gate also establishes a vertical electrical field across a tunneling oxide layer which separates the floating gate from the channel region. This vertical electric field attracts the hot electrons and accelerates them toward the floating gate, which is disposed between the control gate and the channel region, by a process known as drain-side tunneling. The floating gate then accumulates and traps the accumulated charge. Fortunately, the process of charging the floating gate is self-limiting. The negative charge that accumulates on the floating gate reduces the strength of the electric field in the tunneling oxide layer to the point where it is no longer capable of accelerating "hot" electrons from the drain side of the channel region.
As will be understood by those skilled in the art, the accumulation of a large quantity of trapped charge (electrons) on the floating gate will cause the effective threshold voltage (V.sub.th) of the field effect transistor comprising the source region, drain region, channel region and control gate to increase. If this increase is sufficiently large, the field effect transistor will remain in a nonconductive "off" state when a predetermined "read" voltage is applied to the control gate during a read operation (i.e., V.sub.th &gt;V.sub.read). In this state, known as the programmed state, the EEPROM device may be said to be storing a logic 0. Once programmed, the EEPROM device retains its higher threshold voltage even when its power supply is interrupted or turned off for long periods of time.
Reading of the EEPROM device is achieved by applying a predetermined read voltage (V.sub.read) to the control gate, typically via a word line connecting a row of identical EEPROM devices or "cells", and applying a positive bias to the drain region, typically via a bit line connecting a column of identical EEPROM cells. If the EEPROM device is programmed, it will not conduct drain current (I.sub.ds). However, if the EEPROM device has not been programmed (or has been erased), it will heavily conduct. In this state, the EEPROM device may be said to be storing a logic 1. Thus, by monitoring the bit line current, the programmed state (i.e., 1 or 0) of the EEPROM device can be determined.
The EEPROM device may be erased by removing the stored charge from the floating gate. The erasure process can be achieved, for example, by grounding the control gate and applying a positive bias to the substrate (e.g., 10-20 Volts). Accordingly, flash EEPROM devices typically require bulk erasure of large portions of an array of cells since the effects of applying a large substrate bias typically cannot be confined to a single EEPROM cell. Unfortunately, during the erasure process, an "over-erase" condition may occur and render the threshold voltage sufficiently negative that the EEPROM cell is turned-on even without the application of a control gate bias. When this occurs, the EEPROM device will conduct whenever its respective bit line is positively biased; therefore, the reading step may result in a logic error caused by the EEPROM device having a threshold voltage which is too low even after the device has been programmed.
As will be understood by those skilled in the art, the rate of drain-side tunneling during programming operations can be increased by increasing the lateral electric field in the channel and/or the vertical electric field in the tunneling oxide layer. However, low control gate voltages and high drain voltages are typically required to generate high lateral electric fields in the channel region, while exactly the opposite biasing condition--low drain voltage and high control gate voltage--is needed to create large vertical electric fields across the tunneling oxide layer. This conflict makes optimization of a flash EEPROM's programming characteristics difficult. In practice, high drain voltages and high gate voltages are used as a compromise, yet this typically means that an EEPROM device may be operating close to breakdown when programming operations are being performed. A further disadvantage inherent in drain-side channel hot-electron injection devices is the relatively low (e.g., &lt;10.sup.-7) hot-electron injection efficiency (defined as the number of electrons injected into the floating gate relative to the number of electron-hole pairs generated in the device channel), which is present during programming because low injection efficiency typically limits the maximum programming speed. Conventional attempts to increase the programming speed typically involve scaling down the physical dimensions of the devices, however, a reduction in physical dimensions is usually accompanied by a decrease in device yield during processing and a deterioration in the ability of the devices to maintain their programmed or erased state over time.
Referring now to FIG. 1, a stacked-gate flash EEPROM (SG-EEPROM) device according to the prior art will be described. The construction and operation of this EEPROM device is also more fully described in U.S. Pat. No. 4,698,787 to Mukherjee et al. As illustrated by FIG. 1, a stacked-gate EEPROM device may comprise a P-type substrate 1, N-type source and drain regions 3 and 5, respectively, a floating gate electrode 7 and a control gate electrode 9. To perform a programming operation, 0 Volts may be applied to the source region 3, 6 Volts may be applied to the drain region 5 and 12 Volts may be applied to the control gate electrode 9. As described above, these biases typically cause drain-side injection of hot electrons into the floating gate electrode 7. To perform an erase operation, the drain region 5 may be allowed to float electrically, 12 Volts may be applied to the source region 3 and 0 Volts may be applied to the control gate electrode 9. These biases typically cause Fowler Nordheim tunneling of electrons from the floating gate electrode 7 to the source region 3. Unfortunately, high voltages are typically required to program the SG-EEPROM device. The programming speed may also be slow because the rate of hot electron transfer from the drain side of the channel region into the floating gate may be low. The requirement that high voltages be generated typically also means that voltage boosting circuits (e.g., charge pumps) be included to provide the high voltage programming signals, however, such circuits can be relatively large and reduce the available area for memory devices.
To address these limitations associated with stacked-gate EEPROM devices, source-side injection EEPROM (SI-EEPROM) devices have been developed. In particular, an SI-EEPROM device having a select gate is disclosed in an article by A. T. Wu et al. entitled A Source-Side Injection Erasable Programmable Read-Only-Memory (SI-EEPROM) Device, IEEE Electron Device Letters, Vol. EDL-7, No. 9, pp. 540-542, September (1986). FIG. 2 herein is a reproduction of FIG. 2 from the Wu et al. article. In this device, a sidewall select gate electrode 19 is provided adjacent a stacked-gate structure comprising a control gate electrode 17 and a floating gate electrode 15. Opposite the gate electrodes 15-19, a semiconductor substrate 10 (e.g., P-type) is provided so that an inversion-layer channel of charge carriers (e.g, electrons) can be established therein when the device is being programmed. Source and drain regions 13 (e.g., N-type) are also provided. As will be understood by those skilled in the art, the select gate 19 acts as the gate of a select transistor, and the control gate 17 acts as the gate of a sense transistor so that the select transistor is electrically connected in series with the sense transistor. These and other aspects of the SI-EEPROM device are more fully described in U.S. Pat. No. 4,794,565 to Wu et al.
As described in the Wu et al. article, programming operations can be performed by biasing the drain region 13 at V.sub.ds =5 Volts, the select gate 19 at V.sub.sg =2 Volts and the control gate 17 at V.sub.cg =15 Volts. Under these biases, the sense transistor can be expected to operate in its linear region of operation and the select transistor can be expected to operate in its saturation region of operation with pinch-off occurring at an intermediate point in the channel region. Thus, a strong lateral electric field (E.sub.y) can be formed in the channel pinch-off region of the select transistor (i.e. near the source side of the sense transistor) to thereby generate hot electrons at the intermediate point. This is because most of the drain-to-source bias appears across the channel of the select transistor with relatively little voltage drop occurring across the channel of the sense transistor. A strong vertical electric field is also induced at the middle of the channel by the control gate voltage and this increases the programming rate by increasing the probability that hot electrons in the channel will be injected into the floating gate.
Notwithstanding these benefits associated with the SI-EEPROM device of FIG. 2, the fact that the channel length of the split-gate device is the combined length of both the sense transistor and the select transistor means that the unit cell area of the split-gate cell is typically larger than the unit cell area of an otherwise equivalent stacked-gate device. In addition, during the method of forming the split gate cell, the step of etching the gate insulating layer of the select transistor may damage the gate insulating film of the sense transistor. Finally, because it necessary to precisely control the length of the select gate electrode, mask misalignment errors may reduce device yield.
Accordingly, notwithstanding the above described prior art flash EEPROM devices, there still exists a need for EEPROM devices which can be efficiently programmed, have low supply voltage and power consumption requires and have small unit cell size.